The present disclosure is directed to methods and devices for synchronizing data output from two or more memory arrays and, in one embodiment, for synchronizing data and error correaction bits for optimum speed in a memory with on-die error correaction.
Memory devices must perform error-detection to ensure that corrupted data is not output. The preferred protocols are referred to as ECC (Error Correaction Code). ECC allows all single-bit errors in a data word to be corrected during analysis and certain multiple-bit errors to be detected and reported.
Currently, there are disadvantages to ECC. One of the disadvantages with ECC analysis in RAM (Random Access Memory) chips arises because of the time and energy needed to perform the ECC analysis. ECC requires two sets of data: the raw data to be corrected and the ECC data providing corrective information. ECC algorithms are more complicated than other error-detection methods, like parity checking, and the logic delays are longer. This causes an average of 2-3% decrease in performance in real world applications.
One of the problems with lost time and energy stems from aligning the bits for analysis. If the data is analyzed too soon, not all data bits may be present, and the analysis is not accurate. If the data is available for analysis, but not analyzed because some preset period of time has not elapsed, then power and time are wasted. In some prior art configurations, three separate signals are required to enable an ECC analysis, one to signal the data bus to send the raw data to the ECC block, another to signal the ECC bus to send the ECC data to the ECC block, and a third to enable the ECC block. Thus, each set of data must go through two enables before it is analyzed. This may create a situation where the data is not analyzed in a timely manner. Keeping the data in latches beyond when it is ready to be read wastes both time and the energy. Capacitors hold the data, but with leakage inherent over time, the data can also become too weak to read such that the data is no longer useful.
There is therefore a need to be able to analyze data as soon as the last bit, i.e., the slowest bit, of data is available to the ECC logic.